Comparison of Two Implementations of Scalable Montgomery Coprocessor Embedded in Reconfigurable Hardware
نویسندگان
چکیده
This paper presents a comparison of two possible approaches for the efficient implementation of a scalable Montgomery Modular Multiplication (MM) coprocessor on modern Field Programmable Logic Devices (FPLDs). The first implementation uses data path based on traditionally used redundant carry-save adders, the second one exploits standard carry-propagate adder with fast carry chain logic not yet used in fully scalable designs. Both implementations use large embedded memory blocks available in recent FPLDs. Speed and logic requirements comparisons are performed on the optimized designs. The issues of targeting a design specifically for a FPLD are considered taking into account the underlying architecture imposed by the target FPLD technology. It is shown that carrysave adder is not an optimal building block for constrained scalable MM coprocessor in modern FPLDs.
منابع مشابه
Montgomery Multiplication Coprocessor on Reconfigurable Logic
In this paper we introduce a scalable Montgomery Multiplication (MM) coprocessor implemented in reconfigurable hardware. A way of connection to Altera Nios embedded processor and some improvements of design are presented.
متن کاملRsa Implementation on Reconfigurable Hardware
This paper presents an example of using a hardwaresoftware codesign by implementation of the RSA cipher embedded in Field Programmable Logic Devices (FPLDs). The effect of moving the computationally most expensive parts of RSA into an optimized scalable Montgomery Multiplication (MM) coprocessor is analyzed and compared with a pure software solution.
متن کاملMontgomery Multiplication Coprocessor for Altera NIOS Embedded Processor
This paper describes scalable Montgomery Multiplication (MM) coprocessor optimized for Altera NIOS embedded processor implemented in reconfigurable hardware. Features of the NIOS soft processor Avalon Bus are used to connect the coprocessor as a memory mapped peripheral so that the overall performance is improved. Implemented coprocessor performs modular MM with large numbers (up to 4096 bits),...
متن کاملHardware-Software Codesign in Embedded Asymmetric Cryptography Application – a Case Study
This paper presents a case study of a hardware-software codesign of the RSA cipher embedded in reconfigurable hardware. The soft cores of Altera’s Nios RISC processor are used as the basic building block of the proposed complete embedded solutions. The effect of moving computationally intensive parts of RSA into an optimized parameterized scalable Montgomery coprocessor(s) is analyzed and compa...
متن کاملCustom Fpga Cryptographic Blocks for Reconfigurable Embedded Nios Processor
This paper introduces two custom blocks for Nios reconfigurable embedded processor implemented on Altera Field Programmable Gate Arrays (FPGAs). When operations like modular multiplication and modular exponentiation of long integers or other complex algebraic functions are performed on a general-purpose processor they usually consume a lot of processor resources and execution times are not sati...
متن کامل